This invention relates generally to video display terminals and particularly to video display terminals that are capable of displaying video data in different formats.
Video display terminals (VDTs) have come into widespread use as the communication media in computer systems requiring user interaction. Nearly every computer system includes a VDT for displaying information to a user. Generally a VDT displays a screen format of 80 characters per line and 25 lines per screen. There are, however, many occasions when a different format is desired, for example, a format of 132 characters per line on a 25 line screen is common. While many VDTs are capable of producing more than one display format, those of interest to this invention change the number of characters per line, but maintain a fixed number of lines per screen, that is the horizontal and vertical deflection frequencies for the cathode ray tube (CRT) display device remain fixed.
The VDT generally has a high frequency crystal oscillator for establishing system timing. This frequency is referred to as the "dot clock" frequency. VDTs having the capability of providing two different display formats include an additional crystal oscillator for generating a different dot clock frequency and a switching arrangement for changing the dot clock frequency by switching between the two oscillators.
Most VDTs are microprocessor driven and include apparatus for deriving the clock signal for the microprocessor by dividing the dot clock frequency. The microprocessor in turn operates on a controller for generating the required cathode ray tube deflection and video signals. The VDT includes a program display memory, often referred to as a screen memory, that "keeps track of" what is on, or is to be put on, the screen. The microprocessor provides the desired information which is stored in the screen memory and the CRT controller accesses the screen memory and controls the character generator to provide the information for the CRT. Difficulties may be experienced with microprocessor stability when switching between the two different dot clock frequencies. Also, the cost of the two or more crystal oscillators and appropriate switching circuits can be quite high.
For example, in lower cost terminals, the clock frequency for the microprocessor is derived from the dot clock frequency. With certain microprocessors such as the 6502, the 6800, and the 6809 it is possible to have the microprocessor access the screen memory to add or delete characters during one phase of the microprocessor clock and have the controller access the memory for screen display during the other phase. This allows screen memory access without memory contention between the microprocessor and the controller, a desirable condition since memory contention leads to undesired flashes and streaks across the screen. The microprocessor must therefore operate at the character clock frequency and the microprocessor clock must change as the character clock changes. Providing a simple logic switch between two unrelated frequencies may occasionally lead to misoperation of the microprocessor and could even lead to a complete failure of the system. A solution to this problem of switching between the two frequencies would entail additional logic to only switch when the phase relationship was such that the microprocessor would not receive too short, or too long, a clock pulse to prevent misoperation. The addition of these parts plus a crystal oscillator is quite expensive. There is therefore a need in the art for a low cost, multi frequency dot clock generator for a VDT.